Submit Manuscript  

Article Details


Low power wide fan-in domino OR gate using CN-MOSFETs

Author(s):

Deepika Bansal*, Bal Chand Nagar, Brahamdeo Prasad Singh and Ajay Kumar  

Abstract:


In this paper, a pseudo domino configuration has been proposed to improve the leakage power consumption and power delay product (PDP) of dynamic logic with carbon nanotube MOSFETs (CN-MOSFETs). Simulation is done using Synopsys HSPICE simulator with 32nm CN-MOSFET technology provided by Stanford at 500 MHz clock frequency. The simulation results of the proposed technique are validated for the improvement of the domino wide fan-in OR gate as a benchmark circuit. The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60 % as compared to standard domino circuit.

Keywords:

Dynamic logic, carbon nano-tubes, CN-MOSFETs, keeper, stack, charge sharing

Affiliation:

Department of Electronics and Communication Engineering, Manipal University Jaipur, Rajasthan, Department of Electronics and Communication Engineering, National Institute of Technology Patna, Bihar, Department of Electronics and Communication Engineering, Manipal University Jaipur, Rajasthan, Department of Mechatronics Engineering, Manipal University Jaipur, Rajasthan



Full Text Inquiry