Deepika Bansal*, Bal Chand Nagar, Brahamdeo Prasad Singh and Ajay Kumar Pages 1 - 8 ( 8 )
Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and power delay product (PDP) of dynamic logic using carbon nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing.
Results and Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.
Dynamic logic, carbon nano-tubes, CN-MOSFETs, keeper, stack, charge sharing
Department of Electronics and Communication Engineering, Manipal University Jaipur, Rajasthan, Department of Electronics and Communication Engineering, National Institute of Technology Patna, Bihar, Department of Electronics and Communication Engineering, Manipal University Jaipur, Rajasthan, Department of Mechatronics Engineering, Manipal University Jaipur, Rajasthan