Pula Lakshmi Kartik, Kankanala Balakrishna, Musala Sarada and Avireni Srinivasulu* Pages 246 - 254 ( 9 )
Background: Static Random Access Memory (SRAM) is a type of semiconductor memory which is used to store each bit. It is faster compared to the DRAM and also has low power consumption, simplicity and reliability. SRAM plays an important role in the power efficient designs and in minimizing the power dissipation by using voltage scaling methods. It is simulated in Cadence software using CNTFET 32 nm technology. Carbon Nanotube Field Effect Transistor (CNTFET) is a 3 terminal device, namely gate, source and drain. CNTFET utilizes the single carbon nanotube or array of carbon nanotubes as a channel instead of silicon material in MOSFET structure. The carbon nanotubes were first discovered in 1991 by Sumio Iijima. They are very long, thin and smooth cylindrical hollow fibers. They are in a hexagonal pattern of carbon atoms. Carbon Nano Tube Field Effect Transistor has electronic, thermal and structural properties. These properties are similar to CMOS and also that CNTFET has high carrier mobility, i.e. five times faster than CMOS without requiring any extra power.
Methods/Results: A new 7-CNT differential dual port SRAM cell is designed by using CNTFET 32 nm technology. This dual port cell is more efficient with low power consumption compared to the 6T and 8T SRAM cells. It performs read and write operations simultaneously, so that, it is a time saving process because of this cell produces the output at a time. Hence, this cell is very advantageous over 6T and 8T SRAM cell. An improvised differential reference based sense amplifier is designed in CNTFET technology and it is used to sense and amplify the low voltage signal with less delay. These circuits are simulated by using Spectre Cadence with 32 nm CNTFET Technology files with +0.4V. The bit interleaving architecture for the 2×2 matrix of 7-CNT dual port SRAM cell with Sense Amplifier (SA) is designed. This 7-CNT SRAM cell is found better than the conventional SRAM cells. These circuits yield good results compared to the conventional designs.
Conclusion: The bit interleaving architecture for the 2×2 matrix of 7-CNT dual port SRAM cell with Sense Amplifier is designed having less delay and minimum power consumption. The proposed sense amplifier is useful in biomedical applications because of the biomedical signals that operate at very low voltage. Finally, the same can be implemented as a global SRAM cell organization by 7-CNT dual port cell with an improved differential reference based sense amplifier having 256 rows followed by 4 columns of each bit cell.
Carbon nanotubes, SRAM, CNTFET, 7T bit cell, Sense delay, BIT interleaving architecture, Sense Amplifier.
Department of E.C.E, V.F.S.T.R University, Vadlamudi-522213, Guntur, A.P, Department of E.C.E, V.F.S.T.R University, Vadlamudi-522213, Guntur, A.P, Department of E.C.E, V.F.S.T.R University, Vadlamudi-522213, Guntur, A.P, Department of E.C.E, JECRC University, Jaipur-303905, Rajasthan